1. Field of the Invention
The present invention relates to a measurement key used in semiconductor device fabrication and a method of fabricating a semiconductor device using the same. More particularly, the present invention relates to a resist reflow measurement key used for measuring the flow of resist and a method of forming a fine pattern of a semiconductor device using the same.
2. Description of the Related Art
Due to widespread demand for semiconductor devices having an increased processing speed and highly integrated memory devices for use in a wide range of electronic devices, there is a need to develop a circuitry product having a sub-micron size. To satisfy this need in highly integrated devices, efforts to develop an improved photoresist composition have been accelerated. Moreover, efforts to obtain a pattern having more precise dimensions to obtain, in particular, a pattern suitable for a structure having a minimum feature size have been accelerated. To fabricate highly integrated semiconductor devices successfully, it is necessary to form more precisely and finely a photoresist pattern widely used in etch and ion implantation processes. To realize these products, a sensitive photoresist is required. However, use of a sensitive photoresist is necessarily accompanied by an additional process, which is complicated.
In a semiconductor fabrication process using a single layer resist and a 0.13 μm process, ArF lithography technology is used. It is forecast, however, that greater precision and dimension control will be required for a process below 0.10 μm, which will be used in the future.
The wavelength of a light source for exposure directly influences the minimum resolution that can be obtained in an exposure apparatus. For instance, in forming a fine line and space (L/S) pattern, a g-line exposure apparatus has a resolution limit of about 0.5 μm and an i-line exposure apparatus has a resolution limit of about 0.3 μm. The recent trend, however, shows that the device design rule is approaching an L/S measurement value below about 0.2 μm. It is forecast that the allowable minimum feature size in a next generation device design rule will continue to decrease. In particular, in fabricating a highly integrated device that requires a small contact hole having a high aspect ratio in an L/S pattern having a fine critical dimension (CD), or a cell array region of a device, various processes to overcome the resolution limit of exposure apparatuses have been developed. A reflow process using heat is one example of such a process.
In a reflow process using heat, an initial photoresist pattern having formed therein a contact hole, which has a size larger than the CD of a final US pattern or the size of a contact hole to be formed, is first formed. Then, the formed photoresist pattern is heated to a temperature above the glass transition temperature (Tg) of the photoresist and is reflowed to form a fine pattern. The heating reduces the viscosity of the linked photoresist to reflow the photoresist. Thus, the CD of the US pattern or the size of the contact hole is reduced, thereby obtaining a desired fine pattern.
In the reflow process, the CD of the reflowed resist pattern is monitored at the after flow inspection (AFI) stage. The exposure dose is controlled on the basis of the CD value measured in the AFI stage. In the process of controlling the CD of the resist pattern in the aforementioned manner, the amount of time required to monitor the CD of the reflowed resist pattern in the AFI stage is very important because it influences the throughput of the whole exposure process.
Until recently, monitoring the CD of the reflowed resist pattern involved measuring the CD of the reflowed resist pattern using a scanning electron microscope (SEM) in the AFI stage. In other words, in applying the present reflow process using heat, the resist pattern, which is reflowed in the AFI stage, is monitored by an SEM and an exposure dose is controlled on the basis of the monitored result. Thus, it takes a significant amount of time to perform a process that can satisfy a desired CD size since the monitoring in the post-development baking (PDB) step, i.e., in the reflow step of the resist, depends only on the CD measurement using the SEM. As a result, performing the CD monitoring on the entire region of a wafer takes too long, thereby significantly reducing throughput as a size of the wafer increases.